FPGAprince

nibbles, the half byte prince

From bits to bytes.

“just our 2bits”

• Add simulation, verification and test.

• Add tools, vendor and third party. may just be a link……

• Add projects, with real world scenarios.

• Add references, links, add books

• Add bio?

Note

If you stumble upon this, This project is under active development.

Contents

• 1. Introduction
• 2. Fundamentals
  • 2.1. Digital Electronics
    • 2.1.1. Transistors
    • 2.1.2. Bits
    • 2.1.3. Digital Logic
    • 2.1.4. Digital Design
  • 2.2. Numbering System
    • 2.2.1. Representation
      • 2.2.1.1. Decimal
      • 2.2.1.2. Binary
      • 2.2.1.3. Hexadecimal
      • 2.2.1.4. Bit width and range of value
      • 2.2.1.5. Hexidecimal and Binary relationship
      • 2.2.1.6. Negative Representation
      • 2.2.1.7. 1’s complement.
      • 2.2.1.8. And sign and magnitude.
      • 2.2.1.9. Octal
      • 2.2.1.10. Fixed-Point
      • 2.2.1.11. Floating-Point
    • 2.2.2. Binary Arithmetic
      • 2.2.2.1. 2s comp
      • 2.2.2.2. Add/Addition
      • 2.2.2.3. Subtract/Subtraction
      • 2.2.2.4. Multiply/Multiplication
      • 2.2.2.5. Divide/Division
      • 2.2.2.6. sign extension
      • 2.2.2.7. 1s comp
      • 2.2.2.8. sign magnitude
  • 2.3. Hardware Descriptive Language (VHDL or Verilog)
• 3. FPGA
  • 3.1. What is an FPGA
  • 3.2. Why use an FPGA
  • 3.3. When to use an FPGA
    • 3.3.1. FPGA vs MCU vs CPU
    • 3.3.2. FPGA vs GPU
    • 3.3.3. FPGA vs ASIC
    • 3.3.4. SOC
  • 3.4. FPGA Architecture
    • 3.4.1. Configurable Logic Blocks (CLB)
      • 3.4.1.1. Look up Table (LUT)
      • 3.4.1.2. Carry Logic (CL)
      • 3.4.1.3. Multiplexer (MUX)
      • 3.4.1.4. Shift Registers (SRL)
    • 3.4.2. Storage Elements
      • 3.4.2.1. Registers/ Flip Flops (FF)
      • 3.4.2.2. Distributed RAM (LUTRAM)
      • 3.4.2.3. BRAM
    • 3.4.3. IO
    • 3.4.4. Interconnect
    • 3.4.5. Clock MGMT
    • 3.4.6. FPGA Dedicated Hardware
      • 3.4.6.1. DSP (extra)
      • 3.4.6.2. XADC (extra)
      • 3.4.6.3. Tranceivers (extra)
      • 3.4.6.4. Hardprocessor
      • 3.4.6.5. PCIe (extra)
    • 3.4.7. Soft Processor
    • 3.4.8. Metastability
• 4. HDL
  • 4.1. VHDL
    • 4.1.1. libraries and use
    • 4.1.2. entity
      • 4.1.2.1. architecture vs structure vs behavior
    • 4.1.3. component
    • 4.1.4. Object Types
      • 4.1.4.1. Signals
      • 4.1.4.2. Assignment/Assigning
      • 4.1.4.3. Conversions and Cast/Casting
      • 4.1.4.4. resize
    • 4.1.5. process
    • 4.1.6. if else
    • 4.1.7. when else
    • 4.1.8. with select
    • 4.1.9. case
    • 4.1.10. generics
    • 4.1.11. generate
    • 4.1.12. package
    • 4.1.13. record
    • 4.1.14. for loop
    • 4.1.15. arrays
    • 4.1.16. operators
    • 4.1.17. functions
    • 4.1.18. Template
  • 4.2. Verilog
  • 4.3. SystemVerilog
  • 4.4. HDL PT. 2
    • 4.4.1. Register/FlipFlops (FF)
    • 4.4.2. Reset
    • 4.4.3. Inferring and Instantiation
    • 4.4.4. Synthesis/Implementation
    • 4.4.5. Using Dedicated Hardware
    • 4.4.6. Finate State Machine
• 5. Combinatorial Circuits
  • 5.1. Basics
    • 5.1.1. Binary
    • 5.1.2. Logic Functions
    • 5.1.3. Truth Table
  • 5.2. Logic Gates
    • 5.2.1. NOT Gate
    • 5.2.2. AND Gate
    • 5.2.3. OR Gate
    • 5.2.4. XOR Gate
    • 5.2.5. NAND Gate
    • 5.2.6. NOR Gate
    • 5.2.7. XNOR Gate
    • 5.2.8. Negative AND Gate
    • 5.2.9. Negative OR Gate
    • 5.2.10. DeMorgan’s Law
  • 5.3. Circuit Analysis, Implementation and Design
    • 5.3.1. Boolean Algebra
    • 5.3.2. Truth Table
    • 5.3.3. Gate-level Minimization
  • 5.4. Combinatorial Components
    • 5.4.1. Multiplexer
    • 5.4.2. Demultiplexer
    • 5.4.3. Encoder
    • 5.4.4. Decoder
    • 5.4.5. Adder
    • 5.4.6. Subtractor
    • 5.4.7. Comparator
    • 5.4.8. Multiplier
    • 5.4.9. Divide
    • 5.4.10. Shifting?
  • 5.5. Bringing it all together
    • 5.5.1. Parity Gen and Check
    • 5.5.2. Simple ALU
    • 5.5.3. NOTES
      • 5.5.3.1. Unsigned vs Signed Binary
      • 5.5.3.2. Unsigned vs Signed Fixed Point
      • 5.5.3.3. Floating point
• 6. Data Storage Elements
  • 6.1. Latches
    • 6.1.1. Multivibrators
    • 6.1.2. SR Latch
    • 6.1.3. Gated SR Latch
    • 6.1.4. D Latch
  • 6.2. Flip Flops (FF)
    • 6.2.1. Clocking the Control Signal
    • 6.2.2. D Flip Flops (DFF)
    • 6.2.3. Edge triggered latch?
    • 6.2.4. SR Flip Flops
    • 6.2.5. JK Flip Flops
    • 6.2.6. T Flip Flops
  • 6.3. Register
  • 6.4. Memory
    • 6.4.1. Read-Only Memory (ROM)
    • 6.4.2. Random Access Memory (RAM)
      • 6.4.2.1. SRAM
      • 6.4.2.2. DRAM
    • 6.4.3. FLASH
• 7. Sequential Circuits
  • 7.1. Circuit Analysis
  • 7.2. Clocking the Control Signal
  • 7.3. Shift Register
    • 7.3.1. serial in serial out
    • 7.3.2. parallel in serial out
    • 7.3.3. serial in parallel out
    • 7.3.4. parallel in parallel out
    • 7.3.5. sequence detection/detector
  • 7.4. Counters
    • 7.4.1. BCD counters
    • 7.4.2. Gray counters
    • 7.4.3. Ring counters (one hot counter)
    • 7.4.4. Johnson counters
  • 7.5. Clock Divider
  • 7.6. FSM Finite State Machine
    • 7.6.1. State Encoding
• 8. Digital Interfaces and Protocols
  • 8.1. Data
    • 8.1.1. JTAG
    • 8.1.2. UART
    • 8.1.3. SPI
    • 8.1.4. Quad SPI
    • 8.1.5. I2C
    • 8.1.6. SPI vs I2C vs UART
    • 8.1.7. USB
    • 8.1.8. RS232
    • 8.1.9. RS422
    • 8.1.10. RS485
    • 8.1.11. CAN
    • 8.1.12. SERDES
    • 8.1.13. Ethernet
      • 8.1.13.1. 10/100/1G
      • 8.1.13.2. PCS/PMA
      • 8.1.13.3. MAC
      • 8.1.13.4. 10G
      • 8.1.13.5. 40G/50G
    • 8.1.14. PCIe
      • 8.1.14.1. DMA
      • 8.1.14.2. Memory Mapped
      • 8.1.14.3. AXI-4
    • 8.1.15. Wireless
      • 8.1.15.1. Bluetooth
      • 8.1.15.2. WIFI
  • 8.2. Video
    • 8.2.1. VGA
    • 8.2.2. HDMI
    • 8.2.3. Display Port
    • 8.2.4. MIPI CSI-2
    • 8.2.5. MIPI DSI
  • 8.3. Memory
    • 8.3.1. SRAM
    • 8.3.2. DDR
    • 8.3.3. SD
    • 8.3.4. Flash
  • 8.4. Audio
    • 8.4.1. I2S
  • 8.5. Sensors
    • 8.5.1. DAC
    • 8.5.2. ADC
    • 8.5.3. Gyro
    • 8.5.4. Accelerometer
    • 8.5.5. Inertial
    • 8.5.6. Camera
    • 8.5.7. Temp
    • 8.5.8. Display
  • 8.6. Input/Output (IO)
    • 8.6.1. GPIO
      • 8.6.1.1. CMOS
      • 8.6.1.2. TTL
    • 8.6.2. Differential IO
      • 8.6.2.1. LVDS
  • 8.7. Connectors
    • 8.7.1. FMC
    • 8.7.2. HMC
    • 8.7.3. NAND
    • 8.7.4. AXIe
    • 8.7.5. PXIe
    • 8.7.6. SFP
    • 8.7.7. QSFP
    • 8.7.8. FireFly
• 9. Applications
  • 9.1. Signals and System
    • 9.1.1. DSP (Digital Signal Processing)
      • 9.1.1.1. Filter
    • 9.1.2. Image and Video Processing
    • 9.1.3. Image Processing
    • 9.1.4. Video Processing
  • 9.2. Communication
    • 9.2.1. Wired/Wireless
    • 9.2.2. Encoding
    • 9.2.3. Symbol Mapping
    • 9.2.4. Modulation
    • 9.2.5. Demodulating
    • 9.2.6. Decoding
    • 9.2.7. Networking
  • 9.3. Information Theory
    • 9.3.1. Error Detection and correction
    • 9.3.2. BCH Encoder
    • 9.3.3. LDPC Encoder
    • 9.3.4. RS Encoder
    • 9.3.5. CRC
  • 9.4. Artificial Intelligence (AI)
  • 9.5. Control Systems
  • 9.6. Organize…
• 10. Advance
  • 10.1. The Three Pillars
    • 10.1.1. Speed
    • 10.1.2. Area
    • 10.1.3. Power
  • 10.2. Pipelining vs. Registering
    • 10.2.1. Pipeline
    • 10.2.2. Registering
  • 10.3. FIFO
  • 10.4. Clock Domain Crossing
    • 10.4.1. Slower to faster
    • 10.4.2. Faster to Slower
  • 10.5. Reset
    • 10.5.1. Asynchronous Reset vs. Synchronous Reset
  • 10.6. Clocking
  • 10.7. Static Timing Analysis
  • 10.8. Timing Closure
    • 10.8.1. Causes of Timing Violations
      • 10.8.1.1. Logic Delay
      • 10.8.1.2. Net Delay
      • 10.8.1.3. Clock Skew and Uncertainty
    • 10.8.2. Analyzing Violations
    • 10.8.3. Addressing Violations
      • 10.8.3.1. High Cell Delay
      • 10.8.3.2. High Route Delay
      • 10.8.3.3. High Clock Skew or Uncertainty
  • 10.9. Somewhere
  • 10.10. Additional Reading
• 11. Glossary